Why Design For Testability (DFT) in a SerDes? Published 2022-08-27 Download video MP4 360p Recommendations 25:42 HIGH SPEED SERDES (INTRODUCTION) 1:00:33 Design for Test Fundamentals 17:15 How SERDES works in an FPGA, high speed serial TX/RX for beginners 20:56 EDT | compression | LFSR patterns | decompressor 40:15 PCIe 5.0 SerDes Test and Analysis 13:08 Why Ring Oscillator Based PLL? 12:21 SERDES Clocking and Equalization for High-Speed Serial Links, Jack Kenney 43:04 Why SerDes Design Challenges from Impairments? 12:46 Why 2D, 2.5D, up to 3D Silicon Stacking and Advanced Packaging Technologies in TSMC 3DFabric™? 12:43 Why JTOL in a CDR? 1:38:48 Scope of DFT in SoC Designs & Career Opportunities in VLSI Industry 07:40 What is a SerDes and why do I need one? 09:26 Lock up latch | Flip Flop | Design For Test | DFT | Latch | Digital Systems | Design for Test 25:49 11 3 DFT1 - Test Mode Operation (SSF & Delay Test LOS/LOC) 14:06 Why Not A Higher Speed SerDes? 11:57 Why A Redriver or A Retimer in A SerDes? 11:57 Why TX Driver in a SerDes? 45:15 High Speed and RF Design Considerations 12:50 ATE Lab To Fab Similar videos 00:37 How much does a CHIPSET ENGINEER make? 27:26 Data and Test - Adam Cron: Fungible DFT: from Chiplets to Chip 06:00 Whiteboard Wednesdays - An Introduction to IC Test and Modus 11:39 Why Phase Interpolator Based CDR? 06:12 Whiteboard Wednesdays - Scan Compression Fundamentals 04:50 Whiteboard Wednesdays - Diagnostics – What Makes Modus Diagnostics an Industry Leading Tool 32:22 Data and Test - Wu Yang: DFT for 3D IC-Challenges and Solutions 20:15 Tessent Streaming Scan Network (SSN): No-compromise DFT by Peter Orlando, Siemens EDA 20:06 Why a flexible, low-power, and wide-range DisplayPort PMA? 31:20 Road to Chiplets: Architecture - Phil Nigh: Test Challenges & Directions as the Industry moves to... 31:56 Heterogeneous Integration Testability - Sameer Ruiwale: Test Economics in a Disaggregated-Die world 28:44 Road to Chiplets: Architecture - Rob Munoz: Chiplet Architectural Considerations for Adoption and... 11:55 Managing Electronics Systems Design Risk With An Optimized Verification Strategy 12:49 On Chip Clock generation, Parameters of Clock, Generation of two non overlapping clocks 33:21 Chiplet interconnect testing using JTAG boundary scan 59:21 T-SAT || VLSI - Exposure Training || Analog Design Over view 59:05 OCP Virtual Summit 2020: Panel Discussion Open D2D PHYs Panel One PHY to Rule Them All More results